Analytical study of complementary memristive synchronous logic gates

Jean-Michel Portal (1) , Mathieu Moreau (1) , Marc Bocquet (1) , Hassen Aziza (1) , Damien Deleruyelle (1) , Christophe Muller (1) , Yue Zhang (2) , Erya Deng (2) , Jacques-Olivier Klein (2) , Damien Querlioz (2) , Dafiné Ravelosona (2) , Claude Chappert (2) , Weisheng Zhao (3)

1 IM2NP - Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2 IEF - Institut d'électronique fondamentale
3 BUAA - Beihang University

This paper describes an analytical study of synchronous logic gate design based on hybrid structure with MOS and resistive switching non-volatile memories (RS-NVMs). This type of structure allows ultra-low power consumption during power down, while often-used data are saved in RS-NVM cells. The parallel data sensing achieves low-power and fast computation time. The logic gate construction theory, from Boolean equation to hybrid MOS/RS-NVM tree, is deeply detailed. Read and write design guideline, regarding RS-NVM and MOS resistance balance are investigated. Practical implementation is given through transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the concept by using CMOS 40 nm design kit and memory compact models.

Mots clés: Low-Power design; synchronous logic gate; Resistive Switching; complementary cell

Domaines: Sciences de l'ingénieur [physics]; Micro et nanotechnologies/Microélectronique

Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, et al.. Analytical study of complementary memristive synchronous logic gates. 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2013, Brooklyn, United States. ⟨10.1109/NanoArch.2013.6623047⟩. ⟨hal-01745759⟩